Cypress CY8C38 Series Pregnancy Monitor PSoC Development Solution

Pregnancy monitors are implemented by monitoring hormone levels, which are monitored by three standard methods: urine, saliva and body temperature. Each detection requires an analog front end to achieve. This article introduces the use of Cypress’s CY8C38 series to develop pregnancy monitors. Specific scheme, block diagram and CY8C38 series features, block diagram, CY8C38 series typical application circuit diagram and CY8CKIT-001 PSoC development board main characteristics, circuit diagram and bill of materials.

Fertility Monitors are devices that monitor fertility levels by monitoring hormone levels. A fertility monitor may analyze hormone levels in bodily fluids, resistance in bodily fluids, basal temperature, or a combination of these methods. There are three standard methods for monitoring hormone levels:

Urine: Tests for luteinizing hormone surge

Saliva: Detects changing electrolyte levels

Temperature: Monitors basal body temperature to predict cycles

Each of these sensing methods require an analog front end (AFE) to perform the necessary measurements. Fertility Monitors are battery powered devices so active power consumption and sleep current are important considerations. A fertility monitor also includes a Display, memory for storage of fertility reading history, serial communication such as USB. A touchscreen or capsense user interface may also be seen in fertility monitors.

PSoC® 3 and PSoC 5 provide a scalable platform which provides all the requisite circuitry to provide a configurable Fertility Monitor on Chip, including:

• High precision Analog front end, including a 0.1% accurate Voltage reference and up to 20 bits of resolution

• Circuitry for sequencing and driving LED for optical measurement of the test strip and the circuitry for reading the photodiode to create a full optical measurement system

LCD direct drive and control

• Low active and sleep mode power consumption, with full operation down to 0.5V

• CapSense fully integrated


• On chip EEPROM
Cypress CY8C38 Series Pregnancy Monitor PSoC Development Solution
Figure 1. Block diagram of pregnancy monitor

With a unique array of configurable blocks, PSoC®3 is a true system-level solution that provides MCU, memory, analog, and digital peripheral functions on a single chip.

The CY8C38 series provides a new method of signal acquisition, signal processing and control with high precision, high bandwidth and high flexibility. Its analog capabilities cover a wide signal range from thermocouple signals (near DC voltage) to ultrasonic signals. The CY8C38 family can handle dozens of data acquisition channels and analog inputs on each GPIO pin. The CY8C38 series is also a high-performance configurable digital system with interfaces such as USB, multi-master I2C and CAN. In addition to the communication interface, the CY8C38 family features an easy-to-configure logic array, flexible routing to all I/O pins, and a high-performance single-cycle 8051 microprocessor core. With PSoC® Creator™, a hierarchical schematic design entry tool, designers can easily create system-level designs using a library of many prebuilt components and Boolean primitives. Using the CY8C38 family not only enables the integration of analog and digital bills of materials, but also easily incorporates the latest design changes with a simple firmware update.

CY8C38 series features:

􀂄 Single-cycle 8051 CPU core
􀂇 Operating frequency between DC to 67 MHz
􀂇 8×8 multiply and divide instructions
􀂇 Flash program memory, up to 64 KB, 100,000 write cycles, 20-year retention time, various security features
􀂇 Up to 8 KB of ECC or configuration flash
􀂇 Up to 8 KB of SRAM memory
􀂇 Up to 2 KB of EEPROM memory, 1M write cycles, 20-year retention
􀂇 24-channel DMA, multi-layer AHB bus access
• Programmable chained descriptors and priorities
• Supports high-bandwidth 32-bit transfers
􀂄 Low voltage, ultra-low power consumption
􀂇 Wide operating voltage range: 0.5V to 5.5V
􀂇 High efficiency boost regulator (input 0.5V, output 1.8V-5.0V)
􀂇 0.8 mA at 3 MHz, 1.2 mA at 6 MHz, 6.6 mA at 48 MHz
􀂇 Low power modes include:
• 1 μA sleep mode with real-time clock and low-voltage detection (LVD) interrupt
• 200 nA sleep mode, RAM retains data
􀂄 General purpose I/O system
􀂇 28 to 72 I/Os (62 GPIO, 8 SIO, 2 USBIO[1])
􀂇 Routeable from any GPIO to any digital or analog peripheral
􀂇 Any GPIO has LCD direct drive function, capable of driving up to 46×16 segments (Segment)[1]
􀂇 CapSense® support on any GPIO [4]
􀂇 1.2V to 5.5VI/O interface voltage, up to 4 voltage domains
􀂇 Any pin or port can be set to accept an independent maskable IRQ
􀂇 Schmitt Trigger TTL Input
􀂇 All GPIOs can be configured as open-drain high/low, pull-up/pull-down, High-Z or strong output
􀂇 Configurable state of GPIO pins at power-on reset (POR)
􀂇 SIO with 25 mA sink capability
􀂄 Digital Peripherals
􀂇 20 to 24 PLD-based programmable general-purpose digital modules
􀂇 Full CAN 2.0b RX buffers (16) and TX buffers (8)[1]
􀂇 Full Speed ​​(FS) USB 2.0 12 Mbps (with internal oscillator) [1]
􀂇 Up to four 16-bit configurable timer, counter and PWM modules
􀂇 Standard Peripheral Libraries
• 8, 16, 24 and 32-bit timers, counters and PWM
• Many other peripherals listed in the catalog
􀂇 Advanced Peripheral Libraries
• Cyclic Redundancy Check (CRC)
• Pseudo Random Sequence (PRS) generator
• LIN bus 2.0
• Quadrature Decoder
􀂄 Analog Peripherals (1.71V ≤ Vdda ≤ 5.5V)
􀂇 Internal voltage reference is 1.024V±0.1% (14 ppm/°C) at -40°C to +85°C
􀂇 Configurable Delta-Sigma ADC with 12- to 20-bit resolution
• Sample rates up to 192 ksps
• Programmable gain stage: x0.25 to x16
• 12-bit mode, 192 ksps, 70 dB SNR, 1-bit INL/DNL
• 16-bit mode, 48 ksps, 90 dB SNR, 1-bit INL/DNL
􀂇 67 MHz 24-bit fixed-point digital filter block (DFB) for implementing FIR and IIR filters
􀂇 Up to four 8-bit 8 Msps IDACs or 1 Msps VDACs
􀂇 Four voltage comparators with 75 ns response time
􀂇 Up to four unspecified op amps capable of driving 25 mA
􀂇 Up to four configurable multi-function analog modules. Configuration examples include PGA, TIA, mixer, and Sample and Hold
􀂇 CapSense Support
􀂄 Programming, debugging, and tracing
􀂇 JTAG (4-wire) interface, Serial Wire Debug (SWD) (2-wire) interface, and Single Wire Viewer (SWV) interface
􀂇 8 address breakpoints and 1 data breakpoint
􀂇 4 KB instruction trace buffer
􀂇 Supports bootloader programming via I2C, SPI, UART, USB, and other interfaces
􀂄 High Precision, Programmable Clock
􀂇 3 to 62 MHz Internal Oscillator Over Temperature and Voltage Range
􀂇 4 to 33 MHz crystal, capable of crystal PPM accuracy
􀂇 Internal PLL capable of generating clocks up to 67 MHz
􀂇 32.768 kHz monitor crystal
􀂇 Low-power internal oscillator with frequencies of 1 kHz, 33 kHz and 100 kHz
􀂄 Temperature and Package
􀂇 -40℃ to +85℃ Industrial temperature
􀂇 48-pin SSOP, 48-pin QFN, 68-pin QFN, and 100-pin TQFP packages are available

Figure 2. Simplified Block Diagram of CY8C38 Family

Figure 3. CY8C38 Series PSoC Power Supply System Block Diagram

Figure 4. Typical application circuit diagram of CY8C38 series

CY8CKIT-001 PSoC Development Board

The CY8CKIT-001 PSoC® Development Kit provides you a common development platform where you can prototype and evaluate different solutions using any one of the PSoC 1, PSoC 3, or PSoC 5 architectures. This guide and kit gives you a practical understanding of PSoC technology . In addition, the kit gives several example projects with step-by-step instructions to enable you to easily get started developing PSoC solutions. This kit includes PSoC CY8C28, CY8C38, and CY8C55 Family Processor Modules. The CY8CKIT-001 PSoC Development Kit supports projects across the PSoC 1, PSoC 3, and PSoC 5 architectures.

The CY8CKIT-001 PSoC Development Board includes:

The CY8CKIT-001 PSoC Development Kit includes:

■ PSoC Development Board
■ PSoC CY8C28 Family Processor Module
■ PSoC CY8C38 Family Processor Module
■ PSoC CY8C55 Family Processor Module
■ MiniProg3 Programmer and Debug tool
■ USB Cable
■ 12V Power Supply Adapter
■ Wire Pack
■ Printed Documentation
❐ Quick Start
❐ Schematic PSoC Development Board Design
■ Software CD for PSoC 1, which includes
❐ PSoC® Designer™ IDE
❐ PSoC® Programmer™ Software
❐ CY8C28 Data Sheets
❐ Kit Release Notes
❐ Software Release Notes
❐ Example Project Files, Firmware, And Documentation
■ Software CD for PSoC 3 / PSoC 5, which includes
❐ PSoC® Creator™ IDE
❐ PSoC Programmer Software
❐ CY8C38 Data Sheet
❐ CY8C55 Data Sheet
❐ Kit Release Notes
❐ Software Release Notes
❐ Example Project Files, Firmware, And Documentation

Figure 5. CY8CKIT-001 PSoC Development Board Outline Drawing

Figure 6. Circuit diagram of CY8CKIT-001B development board

Figure 7. CY8C28 series processor module circuit diagram

Figure 8. CY8C29 series processor module circuit diagram

Figure 9. CY8C38 series processor module circuit diagram

Figure 10. CY8C55 series processor module circuit diagram

CY8CKIT-001 PSoC Development Board Bill of Materials:

CY8C28 processor module bill of materials:

CY8C29 processor module bill of materials:

CY8C38 processor module bill of materials:

CY8C55 processor module bill of materials:

For details, see:

The Links:   PD10M44OH7B06 LQ190E1LW52