What do you think of when you hear the word “semiconductor“? It sounds complicated and distant, but it has permeated every aspect of our lives: semiconductors are used in everything we rely on in our daily lives, from smartphones, laptops, credit cards to subways.
The manufacture of each semiconductor product requires hundreds of processes, and Lam Group divides the entire manufacturing process into eight steps: wafer processing – oxidation – lithography – etching – thin film deposition – interconnection – testing – packaging.
In order to help you understand and understand semiconductors and related processes, we will introduce each of the above steps one by one in three WeChat pushes.
first step wafer processing
All semiconductor processes start with a grain of sand! Because the silicon contained in the sand is the raw material needed to produce wafers. Wafers are circular slices formed by cutting a single crystal cylinder made of silicon (Si) or gallium arsenide (GaAs). To extract high-purity silicon materials, silica sand, a special material with a silicon dioxide content of up to 95%, is also the main raw material for making wafers. Wafer processing is the process of producing and obtaining the above-mentioned wafers.
The sand is first heated to separate the carbon monoxide and silicon, and the process is repeated until ultra-high-purity Electronic-grade silicon (EG-Si) is obtained. High-purity silicon is melted into a liquid and then solidified into a single-crystal solid form called an “ingot,” the first step in semiconductor manufacturing. The manufacturing precision of silicon ingots (silicon pillars) is very high, reaching the nanometer level, and the widely used manufacturing method is the pulling method.
② Ingot cutting
After the previous step is completed, both ends of the ingot need to be cut off with a diamond saw, and then cut into thin slices of a certain thickness. The ingot flake diameter determines the wafer size, and larger and thinner wafers can be divided into more usable units, helping to reduce production costs. After cutting the silicon ingot, it is necessary to add “flat area” or “dimple” markings on the wafer, so that it is convenient to set the machining direction as a standard in subsequent steps.
③ Wafer surface polishing
The thin slices obtained by the above dicing process are called “bares”, ie unprocessed “raw wafers”. The surface of the die is uneven, and it is not possible to print circuit patterns directly on it. Therefore, it is necessary to first remove surface defects through grinding and chemical etching processes, then to form a smooth surface by polishing, and then to remove residual contaminants by cleaning, and then a finished wafer with a clean surface can be obtained.
The second step is oxidation
The role of the oxidation process is to form a protective film on the wafer surface. It protects wafers from chemical impurities, prevents leakage currents from entering circuits, prevents diffusion during ion implantation, and prevents wafer slippage during etching.
The first step of the oxidation process is to remove impurities and pollutants, and it is necessary to remove impurities such as organics, metals, and evaporation residual moisture through four steps. After cleaning, the wafer can be placed in a high temperature environment of 800 to 1200 degrees Celsius, and the silicon dioxide (or “oxide”) layer is formed by the flow of oxygen or vapor on the surface of the wafer. Oxygen diffuses through the oxide layer and reacts with silicon to form an oxide layer of various thicknesses, whose thickness can be measured after the oxidation is complete.
Dry and wet oxidation
According to the different oxidants in the oxidation reaction, the thermal oxidation process can be divided into dry oxidation and wet oxidation. The former uses pure oxygen to generate a silicon dioxide layer, which is slow but the oxide layer is thin and dense. The latter requires both oxygen and high solubility. of water vapor, which is characterized by a fast growth rate but a relatively thick protective layer and low density.
In addition to the oxidant, there are other variables that affect the thickness of the silicon dioxide layer. First, the wafer structure and its surface defects and internal doping concentrations all affect the rate of oxide formation. In addition, the higher the pressure and temperature generated by the oxidation equipment, the faster the oxide layer will be formed. During the oxidation process, it is also necessary to use dummy wafers according to the position of the wafer in the cell to protect the wafer and reduce the difference in oxidation degree.
The third step photolithography
Lithography is the “printing” of a circuit pattern onto a wafer using light, and we can understand it as drawing a plan on the surface of the wafer needed for semiconductor fabrication. The higher the fineness of the circuit pattern, the higher the integration of the finished chip, which must be achieved through advanced lithography technology. Specifically, photolithography can be divided into three steps: coating photoresist, exposing and developing.
① Coating photoresist
The first step in drawing circuits on a wafer is to apply photoresist over the oxide layer. Photoresist turns the wafer into “photo paper” by changing its chemical properties. The thinner the photoresist layer on the wafer surface, the more uniform the coating, the finer the pattern that can be printed. A “spin coating” method can be used for this step.
According to the difference in light (ultraviolet) reactivity, photoresists can be divided into two types: positive and negative, the former will decompose and disappear after being exposed to light, leaving the pattern of the unilluminated area, while the latter will polymerize after being exposed to light. And let the graphics of the light-receiving part appear.
After the wafer is covered with a film of photoresist, the circuit can be printed by controlling the exposure of light, a process called “exposure.” We can selectively pass light through the exposure equipment, and when the light passes through the mask containing the circuit pattern, the circuit can be printed on the wafer with the photoresist film underneath.
During the exposure process, the finer the print pattern, the more components the final chip can accommodate, which helps improve production efficiency and reduce the cost of individual components. In this area, a new technology that is currently attracting attention is EUV lithography. In February last year, Fanlin Group and its strategic partners ASML and imec jointly developed a new dry film photoresist technology. This technology can greatly improve the productivity and yield of EUV lithography exposure processes by increasing resolution, a key element in fine-tuning circuit width.
The step after exposure is to spray developer on the wafer to remove the photoresist from the areas not covered by the pattern, allowing the printed circuit pattern to emerge. After the development is completed, it needs to be checked through various measuring equipment and optical microscopes to ensure the quality of the circuit diagrams.
The above is a brief introduction to wafer processing, oxidation and lithography. Next, we will introduce two important steps in semiconductor manufacturing – etching and thin film deposition!
Step 4 Etching
After the photolithography of the circuit diagram on the wafer is completed, an etching process is used to remove any excess oxide film and leave only the semiconductor circuit diagram. To do this requires the use of liquid, gas or plasma to remove selected excess.
There are two main methods of etching, depending on the substance used: wet etching, which uses a specific chemical solution to perform chemical reactions to remove oxide films, and dry etching, which uses gas or plasma.
Wet etching using chemical solutions to remove oxide films has the advantages of low cost, fast etching speed and high productivity. However, wet etching is isotropic in that its speed is the same in any direction. This results in the mask (or sensitive film) not being perfectly aligned with the etched oxide film, making it difficult to handle very fine circuit patterns.
Dry etching can be divided into three different types. The first is chemical etching, which uses an etching gas (mainly hydrogen fluoride). Like wet etching, this method is isotropic, which means it is also not suitable for fine etching.
The second method is physical sputtering, which uses ions in the plasma to strike and remove excess oxide layers. As an anisotropic etching method, sputtering etching has different etching speeds in the horizontal and vertical directions, so its fineness is also higher than that of chemical etching. But the disadvantage of this method is that the etching speed is slower, because it completely relies on the physical reaction caused by ion collision.
The final third method is reactive ion etching (RIE). RIE combines the first two methods, that is, chemical etching with the help of free radicals generated after plasma activation while using plasma for ionization physical etching. In addition to the etching speed exceeding the previous two methods, RIE can utilize the characteristics of ion anisotropy to realize the etching of high-definition patterns.
Dry etching has been widely used today to improve the yield of fine semiconductor circuits. Maintaining full-wafer etch uniformity and increasing etch speed is critical, and today’s state-of-the-art dry etch equipment is supporting the production of state-of-the-art logic and memory chips with higher performance.
For different etching applications, Lam Group provides multiple etching product series, including DSiE? series and Syndion? series for deep silicon etching, key dielectric etching products Flex? series, for conductor etching Kiyo? series, Versys? Metal series for metal etching. On the basis of the industry-leading Kiyo and Flex process modules, Lam Group also launched the Sense.i™ series in March last year, its high performance can meet the precision and consistency requirements of the aforementioned production process, suitable for a variety of Critical and semi-critical etch applications.
Step 5 Thin Film Deposition
To create the tiny devices inside the chip, we need to continuously deposit layers of thin films and etch away the excess, as well as add materials to separate the different devices. Each transistor or memory cell is built step-by-step through the above process. The “thin film” we refer to here refers to a “film” with a thickness of less than 1 micrometer (μm, one millionth of a meter) that cannot be fabricated by ordinary mechanical processing methods. The process of placing a thin film containing the desired molecular or atomic unit onto a wafer is called “deposition.”
To form a multi-layered semiconductor structure, we need to create a device stack, that is, alternately stack multiple layers of thin metal (conducting) films and dielectric (insulating) films on the wafer surface, and then repeat the etching process to remove excess parts and form a three-dimensional structure. The techniques that can be used in the deposition process include chemical vapor deposition (CVD), atomic layer deposition (ALD), and physical vapor deposition (PVD), and the methods using these techniques can be divided into dry and wet deposition.
01. Chemical vapor deposition
In chemical vapor deposition, the precursor gases chemically react in the reaction chamber and produce films that adhere to the wafer surface and by-products that are pumped out of the chamber.
Plasma-enhanced chemical vapor deposition requires the use of plasma to generate reactive gases. This approach lowers the reaction temperature and is therefore ideal for temperature-sensitive structures. Using plasma also reduces deposition times, often resulting in higher quality films.
02. Atomic Layer Deposition
Atomic layer deposition forms thin films by depositing only a few atomic layers at a time. The key to the method is to cycle through individual steps in a certain order and maintain good control. Coating the precursor on the surface of the wafer is the first step, and then introducing different gases to react with the precursor can form the desired substance on the surface of the wafer.
03. Physical vapor deposition
As the name suggests, physical vapor deposition refers to the formation of thin films by physical means. Sputtering is a physical vapor deposition method, the principle of which is to sputter the atoms of the target material through the bombardment of argon plasma and deposit them on the surface of the wafer to form a thin film.
In some cases, the deposited film can be treated and improved by techniques such as ultraviolet thermal processing (UVTP).
Lam’s deposition equipment features exceptional precision, performance and flexibility, including the ALTUS® series for tungsten metallization, the SOLA® series with post-film deposition processing capabilities, and the SPEED® series for high-density plasma chemical vapor deposition , Using advanced ALD technology Striker? series and VECTOR? PECVD series and so on.
We have already seen the first few major steps of semiconductor manufacturing, including wafer processing, oxidation, lithography, etching and thin film deposition. We move on to the last three steps: interconnection, testing, and packaging to complete the fabrication of semiconductor chips.
Step 6 · Interconnect
The conductivity of semiconductors lies between conductors and nonconductors (i.e. insulators), a property that allows us to fully control the flow of electricity. Components such as transistors can be built through wafer-based lithography, etching and deposition processes, but they also need to be connected to send and receive power and signals.
Metals are used for circuit interconnection because of their electrical conductivity. Metals used in semiconductors need to meet the following conditions:
Low Resistivity: Since metal circuits need to carry current, the metals in them should have low resistance.
Thermochemical Stability: The properties of metal materials must remain unchanged during metal interconnection.
High reliability: With the development of integrated circuit technology, even a small amount of metal interconnect material must have sufficient durability.
Manufacturing cost: Even if the first three conditions are met, if the material cost is too high, it cannot meet the needs of mass production. The interconnect process mainly uses two substances, aluminum and copper.
Aluminum Interconnect Process
The aluminum interconnect process begins with aluminum deposition, photoresist application, and exposure and development, followed by etching to selectively remove any excess aluminum and photoresist before proceeding to the oxidation process. After the aforementioned steps are completed, the photolithography, etching and deposition processes are repeated continuously until the interconnection is completed.
In addition to its excellent electrical conductivity, aluminum is also characterized by easy lithography, etching and deposition. In addition, it has a lower cost and better adhesion to the oxide film. The disadvantage is that it is easy to corrode and has a low melting point. In addition, to prevent the aluminum from reacting with the silicon causing connection problems, a metal deposit called a “barrier metal” is added to separate the aluminum from the wafer.
Aluminum circuits are formed by deposition. After the wafer enters the vacuum chamber, a thin film of aluminum particles adheres to the wafer. This process is called “Vapor Deposition (VD)” and includes chemical vapor deposition and physical vapor deposition.
Copper Interconnect Process
With the improvement of semiconductor process precision and the reduction of device size, the connection speed and electrical characteristics of aluminum circuits are gradually unable to meet the requirements. For this reason, we need to find new conductors that meet the requirements of both size and cost. The first reason why copper can replace aluminum is that it has lower resistance and therefore enables faster device connection speeds. Second, copper is more reliable because it is more resistant than aluminum to electromigration, which is the movement of metal ions that occurs when an electric current flows through the metal.
However, copper does not easily form compounds, so it is difficult to vaporize and remove it from the wafer surface. In response to this problem, we no longer etch copper, but deposit and etch dielectric material, so that metal circuit patterns consisting of channels and via holes can be formed where needed, and then copper is filled into the aforementioned “” pattern” to achieve interconnection, and the final filling process is called “damascene process”.
As the copper atoms continue to diffuse into the dielectric, the latter becomes less insulating and creates a barrier that blocks further copper atoms from diffusing. A thin copper seed layer is then formed on the barrier layer. After this step, electroplating can be performed, that is, the high aspect ratio pattern is filled with copper. After filling, the excess copper can be removed by metal chemical mechanical polishing (CMP) method, and the oxide film can be deposited after completion, and the excess film can be removed by photolithography and etching process. The entire process described above needs to be repeated until the copper interconnection is completed.
As can be seen from the above comparison, the difference between copper interconnects and aluminum interconnects is that the excess copper is removed by metal CMP rather than etching.
Step 7 Test
The main goal of the test is to check whether the quality of the semiconductor chip reaches a certain standard, thereby eliminating defective products and improving the reliability of the chip. In addition, tested defective products do not enter the packaging step, helping to save cost and time. electronic Die Sorting (EDS) is a test method for wafers.
EDS is a process that inspects the electrical characteristics of individual chips in wafer state and thereby improves semiconductor yield. EDS can be divided into five steps, as follows:
01. Electrical parameter monitoring (EPM)
EPM is the first step in semiconductor chip testing. This step will test every device (including transistors, capacitors, and diodes) that a semiconductor integrated circuit needs to use to ensure that its electrical parameters are up to standard. The primary role of EPM is to provide measured electrical characteristic data that will be used to improve the efficiency of the semiconductor manufacturing process and product performance (not to detect defective products).
02. Wafer aging test
The semiconductor defect rate comes from two aspects, namely the rate of manufacturing defects (higher in the early stage) and the rate of defects occurring throughout the life cycle thereafter. Wafer burn-in test refers to testing the wafer under a certain temperature and AC/DC voltage to find out products that may have defects at an early stage, that is to say, improve the reliability of the final product by discovering potential defects .
After the burn-in test is completed, the semiconductor chip needs to be connected to the test device with a probe card, after which the wafer can be tested for temperature, speed and motion to verify the relevant semiconductor function. See the table for a description of the specific test steps.
Patching is the most important test step, because some bad chips can be repaired by simply replacing the faulty component.
Chips that fail electrical tests have already been sorted out in previous steps, but need to be marked to distinguish them. Whereas in the past we needed to mark defective chips with special inks to ensure they were identifiable with the naked eye, today the system automatically sorts them based on test data values.
Step 8 Packaging
A wafer that has been processed through the previous processes results in square chips of equal size (also known as “single wafers”). The next thing to do is to get the individual chips by dicing. Freshly cut chips are fragile and cannot exchange electrical signals, and need to be handled separately. This process is encapsulation, which involves forming a protective casing around the semiconductor chips and enabling them to exchange electrical signals with the outside world. The entire packaging process is divided into five steps, namely wafer sawing, single die attach, interconnection, molding and package testing.
01. Wafer sawing
To cut countless densely packed chips from a wafer, we first carefully “grind” the backside of the wafer until it is thick enough for the packaging process. After grinding, we can cut along the scribe lines on the wafer until the semiconductor chips are separated.
There are three wafer sawing techniques: blade cutting, laser cutting and plasma cutting. Blade dicing refers to cutting wafers with diamond blades, which is prone to frictional heat and debris that can damage the wafer. Laser cutting is more precise and can easily handle wafers with thin thicknesses or very small scribe line spacing. Plasma dicing uses the principle of plasma etching, so even if the scribe line spacing is very small, this technique can also be used.
02. Single Wafer Attachment
After all the chips are separated from the wafer, we need to attach the individual chips (single wafers) to the substrate (lead frame). The role of the substrate is to protect the semiconductor chips and allow them to exchange electrical signals with external circuits. A liquid or solid tape adhesive can be used to attach the chip.
After attaching the chip to the substrate, we also need to connect the contact points of the two in order to exchange electrical signals. There are two connection methods that can be used in this step: wire bonding using thin metal wires and flip chip bonding using ball gold or tin bumps. Wire bonding is a traditional method, and flip-chip bonding technology can speed up semiconductor manufacturing.
After the connection of the semiconductor chips is completed, it is necessary to use a molding process to add a package to the outside of the chips to protect the semiconductor integrated circuits from external conditions such as temperature and humidity. Once the encapsulation mold is made as required, we place both the semiconductor chip and epoxy molding compound (EMC) into the mold and seal it. The sealed chip is in its final form.
05. Package test
Chips that already have their final form go through a final defect test. All that goes into final testing are finished semiconductor chips. They will be put into test equipment and set different conditions such as voltage, temperature and humidity for electrical, functional and speed tests. The results of these tests can be used to find defects, improve product quality and production efficiency.
Evolution of Packaging Technology
Packaging has undergone several technological innovations over the past few years as chip size has decreased and performance requirements have increased. Some future-oriented packaging technologies and solutions include the use of deposition for traditional back-end processes such as wafer-level packaging (WLP), bumping and redistribution layer (RDL) technologies, and lithography for front-end wafer fabrication. Etching and cleaning techniques.
Below we introduce some advanced packaging solutions developed by Lam Group.
What is advanced packaging?
Traditional packaging requires each chip to be cut from a wafer and placed into a mold. Wafer-level packaging (WLP) is a type of advanced packaging technology that refers to the direct packaging of chips that are still on the wafer. The process of WLP is to first package and test, and then separate all the formed chips from the wafer at one time. The advantage of WLP is lower production cost compared to traditional packaging.
Advanced packaging can be divided into 2D packaging, 2.5D packaging and 3D packaging.
Smaller 2D package
As mentioned earlier, the main uses of the packaging process include sending signals from the semiconductor chip to the outside, and the bumps formed on the wafer are the contact points for sending input/output signals. These bumps are divided into two types: fan-in and fan-out. The fan shape of the former is inside the chip, and the fan shape of the latter is beyond the scope of the chip. We refer to the input/output signal as I/O (input/output) and the number of input/output as the I/O count. The I/O count is an important basis for determining the packaging method. Fan-in packaging is used if the I/O count is low. Since the chip size does not change much after packaging, this process is also known as chip-scale packaging (CSP) or wafer-level chip-scale packaging (WLCSP). If the I/O count is high, a fan-out packaging process is usually used and a redistribution layer (RDL) is required in addition to the bumps for signaling. This is “Fan-Out Wafer Level Packaging (FOWLP)”.
2.5D packaging technology can put two or more types of chips into a single package, while allowing the signal to travel laterally, which can improve the size and performance of the package. The most widely used 2.5D packaging method is to put memory and logic chips into a single package through a silicon interposer. 2.5D packaging requires core technologies such as through-silicon vias (TSVs), micro-bumps, and fine-pitch RDL.
3D packaging technology can place two or more types of chips into a single package while allowing signals to travel longitudinally. This technique is suitable for smaller and higher I/O count semiconductor chips. TSV can be used for chips with high I/O count, wire bonding can be used for chips with low I/O count, and finally a signal system in which chips are arranged vertically. The core technologies required for 3D packaging include TSV and micro bump technology.
Lam Group is able to provide the core solutions required for the above processes, including silicon etch, metal diffusion barrier, copper plating and cleaning technologies, as well as plating, cleaning and wet etching solutions required to build micro bumps and micro RDLs.
So far, the eight steps of semiconductor product manufacturing “wafer processing – oxidation – lithography – etching – thin film deposition – interconnection – testing – packaging” have all been introduced, from “sand” to “chip”, Semiconductor Technology A real-life version of “a touch of stone turns into gold” is being staged.