“Some foundries are still developing new processes based on next-generation gate-all-around transistors, including more advanced high-mobility versions, but bringing these technologies into production will be difficult and expensive. Intel, Samsung, TSMC and others are laying the groundwork for a transition from today’s FinFET transistors to new gate-all-gate field-effect transistors (GAA FETs) at the 3nm and 2nm nodes, which will begin next year or 2023.
Some foundries are still developing new processes based on next-generation gate-all-around transistors, including more advanced high-mobility versions, but bringing these technologies into production will be difficult and expensive. Intel, Samsung, TSMC and others are laying the groundwork for a transition from today’s FinFET transistors to new gate-all-gate field-effect transistors (GAA FETs) at the 3nm and 2nm nodes, which will begin next year or 2023.
GAA FETs will be used below 3nm with better performance, lower power consumption and lower drain voltage. While GAA FET transistors are considered an evolution of FinFET and have been in development for years, any new transistor or material is a huge undertaking for the chip industry. Chipmakers have been delaying the move for as long as possible, but in order to continue scaling transistors, GAA FETs are needed.
It should be pointed out that although they are both nanosheet FETs, there are several types of GAA architectures. Basically, a nanosheet FET is flanked by a FinFET with a gate that wraps around it, enabling higher performance at lower power.
Figure 1: Planar transistors vs. FinFETs and GAA FETs. Source: Lam Research
“GAA technology is critical for the continued scaling of transistors. A key feature of 3nm GAA is that the threshold voltage can be 0.3V. This enables better switching at lower standby power compared to 3nm FinFET,” IBS chief Executive Officer Handel Jones said. “The product design cost of 3nm GAA will not be significantly different from 3nm FinFET. But the IP certification of GAA will be 1.5 times the cost of 3nm FinFET.”
Moving to any new transistor technology is challenging, and the rollout timeline for nanosheet FETs varies from fab to fab. For example, Samsung is mass-producing FinFET-based 7nm and 5nm processes and plans to launch 3nm nanosheets between 2022 and 2023. Meanwhile, TSMC will expand FinFETs to 3nm, while migrating to 2nm nanosheet FETs in 2024/2025. Intel and other companies are also working on nanosheets.
Nanosheet FETs contain multiple components, including a channel that allows electrons to flow through the transistor. The first nanosheet FETs used traditional silicon-based channel materials, but next-generation versions will likely include high-mobility channel materials that allow electrons to move faster in the channel, improving device performance.
High mobility channels are not new and have been used in transistors for years. But these materials present nanosheets with integration challenges that suppliers are taking different approaches to address:
At IEDM (International Electronic Components Conference), Intel presented a paper on nanosheet pMOS devices of strained silicon germanium (SiGe) channel material. Intel developed the device using a so-called “channel first” process.
IBM is developing similar SiGe nanosheets using a different channel-last process.
Other channel materials are in development.
The challenge of chip scaling
As processes evolve, the number of companies capable of manufacturing advanced node chips is shrinking. One of the key reasons is that new nodes are getting more expensive, with TSMC’s state-of-the-art 300mm fab costing $20 billion.
For decades, the IC industry has followed Moore’s Law, doubling transistor density every 18 to 24 months in order to add more functionality on a chip. However, the pace has slowed down as the cost of new nodes has increased. Originally at the 20nm node, when planar transistors have reached their peak performance and need to be replaced by FinFETs, Moore’s Law may slow down further with the introduction of GAA FETs.
FinFETs greatly help improve leakage current at the 22nm and 16/14nm nodes. “Compared to planar transistors, the fins are contacted on three sides through the gate, allowing better control of the channel formed in the fins,” said Nerissa Draeger, project leader at Lam Research University.
Below 7nm, static power is again a serious issue, and power and performance benefits start to diminish. In the past, chipmakers could expect a 70 percent shrinkage in transistor size, a 40 percent increase in performance at the same power, and a 50 percent reduction in area. Now, performance improvements are in the 15-20% range, requiring more complex processes, new materials and different manufacturing equipment.
To keep costs down, chipmakers have begun deploying new architectures that are more heterogeneous than in the past, and they have become increasingly choosy about chips made on the latest process nodes. Not all chips need FinFETs, analog, RF and other devices just need more mature processes and are still in high demand.
But digital logic chips continue to evolve, and transistor structures at 3nm and below are still being developed. The big question is how many companies will continue to fund shrinking transistor R&D, and how, and how well, will these advanced node chips be integrated with more mature processes in the same package or system.
Walter Ng, vice president of business development at UMC, said: “It’s really about wafer economics. At cutting-edge nodes, wafer costs are astronomical, so very few customers and applications can afford the expensive cost. Even for those who can Cost customers, some of their wafer sizes already exceed the reticle maximum size, which obviously creates a yield challenge.”
Both mature nodes and advanced nodes are in high demand. Aki Fujimura, CEO of D2S, said: “The chip industry is divided, and supercomputing needs (including deep learning and other applications) require advanced processes such as 3nm, 2nm, etc. At the same time, the Internet of Things and other high-volume, low-cost applications will Continue to use proven craftsmanship.”
Why use nanosheets?
Cutting edge craftsmanship has several hurdles to overcome. When the fin width reaches 5nm (that is, the 3nm node), the FinFET is approaching its physical limit. FinFETs have reached a limit of about 45nm in contact pitch (CPP) with a metal pitch of 22nm. CPP is the distance from the gate contact of one transistor to the gate contact of an adjacent transistor.
Once FinFETs reach their limits, chipmakers will migrate to nanosheet FETs of 3nm/2nm and beyond. Of course, FinFETs are still available for 16nm/14nm to 3nm chips, and planar transistors are still the mainstream technology at 22nm and beyond.
Omni-directional gates are different from FinFETs. Lam’s Draeger explained: “The all-purpose gate or GAA transistor is a modified transistor structure in which the gate contacts the channel from all sides and enables further scaling. Early GAA devices will use vertically stacked nanosheets. They are composed of individual It consists of a horizontal plate, surrounded by gate material on all sides. It provides improved channel control relative to FinFETs.”
In nanosheet FETs, each platelet constitutes a channel. Both pFET and nFET devices of the first generation of nanosheet FETs will be silicon-based channel materials. Second-generation nanosheets will likely use high-mobility materials for pFETs, while nFETs will continue to use silicon.
Nanosheet FETs consist of two or more sheets. Recently, Letti demonstrated a nanoFET with 7 slices. Sylvain Barraud, senior integration engineer at Leti, said in the paper that the seven-chip GAA offers a 3x performance improvement over the usual 2-level stacked nanoplate GAA transistors.
On the surface, the scaling advantage of 3nm FinFETs over nanosheets seems small. Initially, a nanosheet FET might have a 44nm CPP with a gate length of 12nm.
However, nanosheets have many advantages over FinFETs. With FinFETs, the width of the device is deterministic. However, with nanosheets, IC suppliers have the ability to vary the width of the sheets in transistors. For example, nanosheets with wider sheets provide higher drive current and performance. Narrow nanosheets have less drive current and occupy less area.
Sri Samavedam, senior vice president of CMOS technology at Imec, said: “GAA architecture further improves short-channel control for shrinking gate lengths, while stacked nanosheets increase drive strength per unit area.”
In addition to the technological advantages, foundries are also developing nanosheet FETs, making choices difficult for customers.
As things stand, Samsung plans to launch the world’s first 3nm nanosheets in 2022/2023. “There is a 50% probability of risk pilot production in the fourth quarter of 2022. There is a 60% probability of high volume production in Q2 to Q3 2023.” IBS’ Jones said.
Using new transistors comes with some cost and time-to-market risks. With this in mind, customers have other options. For example, TSMC plans to expand FinFETs to 3nm before using nanosheets.
“Samsung is clearly the leader in 3nm GAA, but TSMC is also developing 2nm GAA for production in 2024-2025,” Jones said. “TSMC has excellent marketing skills and has attracted many large customers to its 3nm FinFET technology.”
In any case, the cost of developing chips on 5nm/3nm and beyond is astronomical. Therefore, customers are looking for alternatives such as advanced packaging.
“As chip size shrinks and it becomes increasingly difficult to use smaller transistors at new nodes, the focus has shifted, such as lower power consumption, higher speed in advanced packaging.” Subodh Kulkarni, President and CEO of CyberOptics .
Fabrication of nanosheets
In the future, leading IC suppliers will migrate to GAA architectures such as nanosheets, which will face many challenges.
“Just like the transition from planar to FinFET, the transition from FinFET to GAA will be difficult,” said David Fried, vice president of computing products at Lam Research. “When moving to FinFETs, the biggest challenge is optimizing the device on the vertical sidewalls, so there are a lot of surface treatment and deposition challenges. Now, with GAA, you have to optimize the device at the bottom layer of the structure. Surface treatment and deposition will become more challenging. “
Etching, a process that removes material from transistor structures, is also more challenging today. “With planar structures, it’s often clear when you want an isotropic (conformal) process rather than an anisotropic (directional) process,” Fried said. “It gets a little trickier with FinFETs. With GAA, this problem becomes It’s very tricky. Some processes require isotropy in places, like etching under the nanowire/sheet and anisotropy, which is extremely challenging.”
In the process flow, nanosheet FETs start by forming a superlattice structure on a substrate. Epitaxy tools deposit alternating layers of SiGe and silicon on the substrate. At least three layers of SiGe and three layers of silicon are stacked.
The next step is to fabricate tiny vertical fins in the superlattice structure. Each nanosheet is separated from each other with spaces between them. In the fab process, the fins are patterned using extreme ultraviolet (EUV) lithography, followed by an etch process.
Scott Hoover, senior director of strategic product marketing at Onto Innovation, said: “GAA transistors perform only better than their weakest channel, so a separate nanosheet size control metric is required. Forming fins through superlattices requires control over thickness, composition, and silicon wafers. CD for individual layer control.”
Then comes one of the more difficult steps – the formation of internal spacers. First, the outside of the SiGe layer in the superlattice structure is recessed using a lateral etching process. This creates a small space and is filled with dielectric material.
Robert Clark, a TEL technician, said: “Controlling the process variation of the internal spacer groove etch is very difficult because the etch cannot be stopped. Ideally, only the epitaxial layer of metal passes through the sidewall spacer. Recessed in place, and then replaced that epitaxial layer with a dielectric internal spacer layer. This is a very critical 5nm recess etch because it is non-linear and cannot be stopped, and it is as difficult as a tightrope process.”
There are other challenges. “The internal spacer module is critical in defining the final transistor function, and control of this module is critical to minimize transistor variability. The internal spacer module controls the effective gate length and connects the gate to the source/drain epi isolation,” said Andrew Cross, director of process control solutions at KLA. “In this module, the SiGe is recessed and then an internal spacer layer is deposited and recessed. During each step of the internal spacer formation, the recess is precisely controlled. And the shape and CD of the final spacer recesses are critical to ensuring transistor performance. Also, each individual channel in the stack needs to be controlled.”
Next, the source/drain is formed, followed by the channel. This requires the use of an etching process to remove the SiGe layer in the superlattice structure, leaving behind the silicon base layer or sheet that forms the channel.
“This step is the separation of the GAA structures from each other, which can lead to challenging defects such as residues between nanosheets, damage to the nanosheets, or selective damage to the source/drain adjacent to the nanosheets themselves.” Cross Say.
The challenges don’t stop there. “The formation of the trench requires individual control of board height, corner corrosion and trench bowing,” said Onto’s Hoover.
High-k/metal gate material is deposited in the structure, and finally copper interconnects are formed to form nanosheet FETs. “Other modules that may change are the bottom isolation of the device and the functional metals/layers used to accommodate the nanosheets, but these modules rely heavily on processes known/developed in the industry.
Of course, it’s getting harder to implement, if not a completely new module.
high mobility device
The first generation of nanosheet FETs will be silicon-based channels. These nanosheets are theoretically superior to FinFETs, but not always.
“From FinFETs to nanosheets, we’ve observed a significant increase in electron mobility (for nFETs). The problem will be a drop in hole mobility in pFETs. That’s what we need to address,” said Nicolas, IBM Device and Cell Process R&D Manager Loubet said in his speech.
In other words, chipmakers need to improve pFET performance in nanosheets. As a result, suppliers are developing second-generation nanosheet FETs with improved pFETs. The second generation of nanosheets will continue to provide silicon-based channels for nFETs because they are able to provide adequate performance.
To improve pFETs, chipmakers are investigating high-mobility channel materials. The more dominant material is SiGe, while III-V materials, germanium and others are also being developed.
“Strained SiGe has recently emerged as a promising pFET channel to replace silicon due to its excellent hole mobility, and a mature process that allows for volume production,” Ashish Agrawal, a device engineer at Intel, said in the paper.
To incorporate these materials, chipmakers implement a so-called strain engineering process in the fab. Strain is a stress applied to silicon to improve electron mobility.
The strain engineering process is not new, and chipmakers have been using SiGe alloy stress in the channel for years to improve carrier mobility. IBM Senior Fellow Shogo Mochizuki said: “Strain engineering has become one of the key technologies in CMOS technology. Beginning at the 90nm node, source-drain epitaxial growth strains in the channel, facilitating electron migration. Moreover, in FinFETs still used.”
So it is natural for chipmakers to introduce strained SiGe channel materials in next-generation GAA transistors, but with some new challenges.
“We propose to replace the channel silicon with channel SiGe, which can help increase mobility. In addition, this innovative technology has enabled ultra-low threshold devices to achieve superior reliability that cannot be provided by the basic strain technology of source-drain epitaxy. ” said Mochizuki. “The biggest challenges for nanosheets using novel channel materials are ensuring material uniformity and structural integrity, as well as ensuring that the novel channel materials are compatible with the process.”
On top of that, there are several ways to develop a SiGe pFET channel, including forming the channel first and then forming the channel.
At IEDM, Intel published a paper on SiGe nanosheet pMOS devices on strain relaxation buffers (SRBs). The nanosheet channel is based on a mixture of compressively strained SiGe and Si0.4Ge0.6. The pMOS device consists of a 5nm sheet thickness and a 25nm long gate.
Channel formation occurs in the early stages of conventional nanosheet processing. In many ways, this is SiGe channel priority.
Intel’s process begins with a 300mm substrate on which a SiGe-based SRB layer is grown. Then, alternating layers of compressive Si0.4Ge0.6 and tensile Si are grown on the SRB layer.
This creates a superlattice structure that forms the basis of the pFET’s SiGe channel. “In this work, we demonstrate a buried Si0.7Ge0.3 SRB bulk stressor that induces compressive strain in Si0.4Ge0.6 pFET nanosheets to enhance holes,” said Intel’s Agrawal. transmission.”
Another term for SRB is virtual substrate. Traditionally, the silicon substrate determines the lattice constant of all epitaxial layers deposited or grown on top of it.
The nature of the strain in the channel and source/drain depends on the relative difference in lattice constant of the layer with respect to the silicon substrate. “For an SRB or dummy substrate, we change the lattice constant of the substrate itself by growing a relaxed Si0.7Ge0.3 buffer layer on top of the silicon substrate,” Agrawal said. All subsequent layers deposited on top of this buffer layer will be relative to Si 0.7 Ge 0.3 strain. By changing the substrate lattice constant of the relaxed Si 0.7 form Ge 0.3 buffer, we can achieve strained nanosheet CMOS.”
Other companies take a different approach. For example, at IEDM, IBM published a paper on nanosheet pFETs with strained SiGe channels using a channel-after-process process.
Using this approach, IBM’s pFET nanosheets have a 100% increase in peak hole mobility and a corresponding 40% reduction in channel resistance, while keeping the slope of the secondary voltage value below 70mV/dec.
Figure 3: Cross-sectional STEM image and EDX elemental map of the stacked SiGe NSs channel epitaxially grown 4 nm thick Si0.65Ge0.35 along gate pillar M1. Wsheet = 40nm. Source: IBM
IBM forms the SiGe trenches later in the process rather than at the beginning. “We realized that starting SiGe growth epitaxy early in the process was ineffective against strain. This also introduced complexity and cost to the manufacturing process,” IBM’s Mochizuki said. “With our new technique, the strain in the SiGe layer is preserved. This happens because this process is based on a SiGe epitaxy backward scheme, which is critical for improved performance.
More specifically, IBM developed the SiGe channel after the channel release process. After the channel is released, the silicon nanosheets are trimmed horizontally and vertically. Then, a layer of SiGe, called the SiGe capping layer, is selectively wrapped around the trimmed silicon nanosheets. “The final structure is a SiGe cladding layer with a thin silicon nanosheet core,” Mochizuki said. “By confining the carriers within the SiGe capping layer, the carrier mobility can be improved in the strained SiGe channel layer.”
GAA FETs face several manufacturing challenges and are so expensive that it’s unclear how many chipmakers can afford them. Fortunately, it’s not the only option. Advanced packaging and new architectures are sure to play a bigger role in current and future devices.
No one technology can meet all needs. So, at least for now, these are options.
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