digital potentiometer(digiPOT) are often used to easily adjust the AC or DC voltage or current output of sensors, power supplies, or other devices that require some type of calibration, such as timing, frequency, contrast, brightness, gain, and offset adjustment. Digital settings avoid virtually all issues associated with mechanical potentiometers, such as physical size, mechanical wear, wiper settings, resistance drift, and sensitivity to vibration, temperature, and humidity, as well as inflexibility of layouts caused by the use of screwdrivers .
digiPOT has two modes of use, potentiometer mode orvariable resistormodel. Figure 1 shows the potentiometer mode. At this time, there are 3 terminals. The signal is connected through the A terminal and the B terminal, and the W terminal (cursor-like) provides an attenuated output voltage. The wiper is normally connected to terminal B when the digital ratio control input is all zeros.
Figure 1. Potentiometer Mode
When the wiper is hardwired to either end, the potentiometer becomes a simplevariable resistor, as shown in picture 2. Fewer external pins are required in variable resistor mode, resulting in a smaller size. Some digiPOTs only have variable resistor mode.
Figure 2. Variable Resistor Mode
There is no limit to the current or voltage polarity at the digiPOT resistor terminals, but the amplitude of the AC signal cannot exceed the power supply rails (VDD and VSS) when the device operates in variable resistor mode, especially in low resistance settings, the maximum current orcurrent density, should be restricted.
typical application
Signal attenuation is inherent in potentiometer mode because the device is essentially a voltage divider. The output signal is defined as: VOUT = VIN × (RDAC/RPOT), in RPOTis the nominal end-to-end resistance of the digiPOT, RDAC is the digitally selected resistance between the W terminal and the input signal reference pin, the reference pin is usually the B terminal, as shown in Figure 3.
Figure 3. Signal Attenuator
Signal amplification requires active components, usually inverting or non-inverting amplifiers.With the appropriate gain formula, either potentiometer mode or variable resistor mode can be used
Figure 4 shows a non-inverting amplifier, where the digiPOT acts as a potentiometer, and the gain can be adjusted by feedback. Since part of the output will feedback, RAW/(RWB +RAW), should be equal to the input, and the ideal gain is:
Figure 4. Noninverting Amplifier in Potentiometer Mode
The gain of this circuit is the same asRAW, inversely proportionalRAWIt rises rapidly as it approaches zero, showing a hyperbolic transfer function characteristic.To limit the maximum gain, insert a resistor withRAW(in the denominator of the gain formula) in series
If a linear gain relationship is desired, the variable resistor mode can be used with fixed external resistors, as shown in Figure 5. The gain is now defined as follows:
Figure 5. Noninverting Amplifier in Variable Resistor Mode
Best performance is obtained by connecting the low capacitance terminal (W pin in newer devices) to the op amp input.
Advantages of digiPOT for signal amplification
The circuits shown in Figures 4 and 5 have high input impedance and low output impedance and can work with unipolar and bipolar signals. The digiPOT can be used for vernier operation to provide higher resolution in a smaller range with fixed external resistors, and can also be used in op amp circuits with or without signal inversion. Additionally, the digiPOT has a low temperature coefficient, typically 5 ppm/°C in potentiometer mode and 35 ppm/°C in varistor mode.
Limitations of digiPOT for signal amplification
When dealing with AC signals, the performance of digiPOT is limited by bandwidth and distortion. Due to parasitic components, the bandwidth is the maximum frequency that can pass through the digiPOT with less than 3 dB of attenuation.total harmonic distortion (THD) (defined here as the ratio of the sum of the rms of the last four harmonics to the fundamental value of the output) is a measure of the attenuation of a signal as it passes through the device. The performance limits covered by these specifications are determined by the internal digiPOT architecture.Through analysis, we can better understand these specifications comprehensively and reduce their negative
The internal architecture has evolved from a traditional series resistor array (as shown in Figure 6a) to a segmented architecture (as shown in Figure 6b). The main improvement is to reduce the number of internal switches required.The first case uses a serial topology with a number of switches ofN = 2nis the number of bits of resolution. n = 10, 1024 switches are required
Figure 6. a) traditional architecture, b) segmented architecture
Proprietary (patented) segmented architecture with cascading connections minimizes the total number of switches. The example in Figure 6b shows a two-stage architecture consisting of two types of blocks, the MSB on the left and the LSB on the right.
The upper and lower modules on the left are a series of switches (MSB segment) for coarse adjustment of the number of digits. The right module is a string of switches (LSB segment) for fine-tuning the number of bits. MSB switch close to R after coarse adjustmentA/RBCompare. The total resistance of the LSB string is equal to a single resistive element in the MSB string, and the LSB switch can be ratio-finely tuned to any point on the main switch string. The A and B MSB switches are complementary.
The number of switches for the segmented architecture is:
N = 2m + 1 + 2n – m,
where n is the total number of bits and m is the number of bits of resolution for the MSB word.For examplen = 10 and m = 5, then 96 switches are required.
The segmented approach requires fewer switches than traditional switch strings:
The number of switches that differ between the two = 2n – (2m + 1 + 2n – m)
In this example, the amount saved is
1024 – 96 = 928!
Both architectures must choose switches with different resistance values, taking into account the sources of ac error in the analog switches. These CMOS (Complementary Metal Oxide semiconductor) switches consist of parallel P-channel and N-channel MOSFETs. This basic bidirectional switch can maintain a fairly constant resistance (RON) signal up to the full supply rail.
bandwidth
Figure 7 shows the parasitic devices that affect the AC performance of a CMOS switch.
Figure 7. CMOS switch mode.
CDS = drain-source capacitance; CD = drain-gate + drain-bulk capacitance; CS = source-gate + source-bulk capacitance.
The transitive relationship is defined by the following formula, which contains the assumptions:
- The source impedance is 0 Ω
- No external load influence
- no fromCDSImpact
- RLSB << RMSB
in:
RDACis the setting resistance
RPOTis the end-to-end resistance
CDLSBis the total drain-gate + drain-bulk capacitance of the LSB segment
CSLSBis the total source-gate + source-bulk capacitance of the LSB segment
CDMSBis the drain-gate + drain-bulk capacitance of the MSB switch
CSMSBis the source-gate + source-bulk capacitance of the MSB switch
moffis the number of disconnect switches in the MSB path of the signal
monis the number of on-off switches of the signal MSB path
The transfer formula is affected by various factors and has a certain relationship with the code, so we simplify the formula with the following additional assumptions
CDMSB + CSMSB = CDSMSB
CDLSB + CSLSB >> CDSMSB
(CDLSB + CSLSB) = CW (see data sheet for details)
The CDShas no effect on the transfer formula, but since it usually occurs much higher than the poleRC The low pass filter is the main response. The ideal approximate simplified formula is:
bandwidth(BW)defined as:
inCLis the load capacitance.
The BWCode dependent, worst case is when the code is at half scale, the AD5292’s digital value is 29= 512, the digital value of AD5291 is 27 = 128 (see Table of Contents). Figure 8 shows the low-pass filtering effect, which is code dependent and varies with different nominal resistance and load capacitance values.
Figure 8. Maximum Bandwidth vs. Load Capacitance for Various Resistor Values
The parasitic trace capacitance of the PC board should also be considered, otherwise the maximum bandwidth will be lower than the expected value. The trace capacitance can be simply calculated using the following formula:
in
εRis the dielectric constant of the sheet
Ais the trace area (cm2)
dis the layer spacing (cm)
For example, assuming that the FR4 board has two signal layers and a power/ground layer, εR = 4, trace length = 3 cm width = 1.2 mm, layer spacing = 0.3 mm; t then the total trace capacitance is about 4 pF.
distortion
THD is used to quantify the nonlinearity of the device as an attenuator.This nonlinearity is determined by the internal switch and its on-resistance as a function of voltage RONproduced. Figure 9 shows an example of amplified amplitude distortion.
Figure 9. Distortion
Compared to a single internal passive resistor, the switch’sRONsmall, and its variation within the signal range is even smaller. Figure 10 shows typical on-resistance characteristics.
Figure 10. CMOS Resistors
The resistance curve depends on the supply voltage rail, at the maximum supply voltage, the internal switchRON Change is minimal. When the supply voltage drops,RON Variation and nonlinearity will increase with it.Figure 11 compares the low voltage digiPOT at two supply levels RON
Figure 11. Switch Resistance Change vs. Supply Voltage
HD depends on a variety of factors and is therefore difficult to quantify, assuming RON, the change is 10%, the following formula can be used for approximate calculation:
In general, the nominal digiPOT resistance (RPOT), the larger the denominator, the smaller the THD.
trade off
RPOTAs it increases, both distortion and bandwidth decrease, so improving one metric necessarily sacrifices the other. Therefore, circuit designers must make an appropriate trade-off between the two. This is also relevant to the design level of the device, as IC designers must balance various parameters in the design formula:
in
COX is an oxide capacitor
μ is the migration constant of electrons (NMOS) or holes (PMOS)
Wis the width
Lis the length
Bias
From a practical point of view, we must take full advantage of each feature. When the digiPOT attenuates an AC signal through capacitive coupling, the distortion is minimal if the signal bias reaches the midpoint of the power supply. This means that the switch operates at the most linear part of the resistive characteristic.
One method is to use dual power supplies, simply ground the potentiometer to the common mode side of the power supply, and the signal will swing positive and negative.If a single power supply is required, or some digiPOTs do not support dual power supplies, another method can be used, that is, adding VDD/2 of the offset voltage to the AC signal. This offset voltage must be added to the two resistor terminals as shown in Figure 12.
Figure 12. Single Supply AC Signal Conditioning
If a signal amplifier is required, a dual-supply inverting amplifier is preferred over a non-inverting amplifier (as shown in Figure 13) for two reasons:
- THD performance is better because the virtual ground of the inverting pin concentrates the switch resistance in the middle of the voltage range.
- Because the inverting pin is at virtual ground, the wiper capacitor C is almost eliminatedDLSB, so that the bandwidth increase is small (the stability of the circuit must be paid attention to).
Figure 13. Adjustable Amplification Using Inverting Amplifier digiPOT
Appendix – About the AD5291/AD5292
256/1024-bit digital potentiometer with 1% accuracy, programmable 20 times
The AD5291/AD5292 digital potentiometers, shown in Figure 14, have 256/1024-bit resolution.End-to-end resistances are available in 20 kΩ, 50 kΩ, and 100 kΩ with better than 1% error and a temperature coefficient ofvariable resistor35 ppm/°C in mode,voltage divider 5 ppm/°C (ratio) in mode. These devices perform the same Electronic adjustment functions as mechanical potentiometers, but in a smaller size and more reliable. Its wiper position can be adjusted via an SPI-compatible interface. Unlimited adjustments are possible before the fuse is blown and the vernier position is fixed (a process similar to applying epoxy to a mechanical adjuster). The “remove epoxy” process can be repeated up to 20 times. The AD5291/AD5292 operate from a single 9 V to 33 V supply or a dual ±9 V to ±16.5 V supply and consume 8 μW. Offered in a 14-pin TSSOP package, the operating temperature range is –40°C to +105°C (back to text)
Figure 14. AD5291/AD5292 Functional Block Diagram
The Links: VVZ175-16IO7 PM200DSA120
