“I participated in a 2.5D silicon interlayer analysis meeting at the 2020 Design Conference. Like many demonstrations at this show, ecosystem collaboration is a major focus. At this meeting, Hu Jinsong, Cadence’s chief application engineer, and He Yongsong, a senior engineer from Enflame, presented methods for inserter power modeling and HBM power noise prediction. Although the focus of application is artificial intelligence, the proposed modeling method has wide applicability.
I participated in a 2.5D silicon interlayer analysis meeting at the 2020 Design Conference. Like many demonstrations at this show, ecosystem collaboration is a major focus. At this meeting, Hu Jinsong, Cadence’s chief application engineer, and He Yongsong, a senior engineer from Enflame, presented methods for inserter power modeling and HBM power noise prediction. Although the focus of application is artificial intelligence, the proposed modeling method has wide applicability.
Enflame Tech is a start-up company with R&D centers in Shanghai and Beijing. They are developing AI training platform solutions, including deep learning accelerators, PCIe boards and software stacks, and target cloud service providers and data centers.
Since the focus of this design is AI training, there is a 4-hi HBM2 memory stack on the car to store training data. ASIC is integrated with HBM2 through silicon interposer. ASIC contains a single integrated hard macro physical quantity, it has 8 independent channels, the total DQ width is 1024, and the total number of signals is 3300 +.
The two key elements of this project are the design and simulation of the interposer. In terms of signal integrity, the length of the wire between HBM and PHY is carefully selected, because longer lengths require stronger drivers. High-speed signal routing is at M1/M3, and the shielding layer is at M2. All signal routings are designed with a line length difference of ±0.15%. The optimized physical configuration includes signal width, track pitch and shielding pattern, as shown in the figure below.
AI chips have a large number of HBM molds for parallel computing, and due to the significant scale of micro-bump and C4 bumps, it brings a certain degree of modeling difficulties for physical design and simulation engineers. For the power modeling aspect of the complete inserter design, use the Cadence Cadence Sigrity XcitePI extraction tool to extract the SPICE netlist model. Model post-processing can verify z impedance, IR voltage drop and time domain power ripple, as shown in the figure below.
Power noise is the key to ensuring the stability of the HBM bus. At the same time, processing huge HBM network system signals and power simulation is also a challenge for current tools. The report of the design conference proposed two innovative methods for predicting HBM power noise, using Cadence Sigrity SystemSI and System Explorer tools for system time domain simulation. The voltage multiplication method and the current induction method are used for further power noise prediction. The figure below is a typical scenario. (The acronym for “CMF” means “current multiplier”.)
The benchmark test is carried out through a test chip mounted on the reference board. The test results show that the simulation prediction and the prediction data have a good correlation.
In summary, these power modeling and noise prediction techniques can be widely used in many different types of 2.5D HBM-based silicon intercalation designs.
Further reading-IR drop
IR voltage drop is a phenomenon in which the voltage on the power supply and ground network in the integrated circuit drops or rises. With the evolution of semiconductor technology, the width of the metal interconnection line becomes narrower and narrower, resulting in an increase in its resistance value, so there will be a certain IR drop across the entire chip. The magnitude of the IR voltage drop is determined by the magnitude of the equivalent resistance from the power supply PAD to the calculated logic gate unit.
The current of each logic gate unit in the SoC design will cause varying degrees of IR drop to other logic gate units in the design. If the logic gate unit connected to the metal wire is flipped at the same time, the resulting IR voltage drop will be very large. However, it is very important to flip some parts of the design at the same time, such as the clock network and the registers it drives. In a synchronous design, they must flip at the same time. Therefore, a certain degree of IR pressure drop is inevitable.
The IR drop may be local or global. When a certain number of logic gate units in adjacent positions have logic flipping actions at the same time, it will cause a local IR voltage drop phenomenon, and when the resistance value of a certain part of the power grid is extremely high, for example, when R14 is far beyond the expected, it will also Causes a local IR voltage drop; when a logic action in a certain area of the chip causes IR voltage drop in other areas, it is called a global phenomenon.
The performance of the IR drop problem is often similar to some timing and may even be a signal integrity problem. If the global IR voltage drop of the chip is too high, the logic gate will have a functional failure, making the chip completely ineffective, although the logic simulation shows that the design is correct. The local IR voltage drop is more sensitive. It can only happen under certain conditions. For example, all bus data is flipped synchronously, so the chip will intermittently show some functional failures. The general effect of IR drop is to reduce the speed of the chip. Experiments have shown that a 5% IR voltage drop on the logic gate unit will reduce the normal gate speed by 15%.