Synopsys Expands DesignWare Security and Processor IP Solutions to Address Information and Functional Security Requirements in Automotive Design

Synopsys, Inc. (Nasdaq: SNPS) today announced new DesignWare® tRoot™ Hardware Security Module (HSM) and ARC® SEM130FS functional and information security processor IP solutions, both integrated Functional safety features to accelerate ISO 26262 certification of automotive systems-on-chips (SoCs). ASIL B compliant automotive tRoot HSMs add hardware security mechanisms to protect against permanent, transient and latent failures of their security systems, including ARC processors, scalable cryptographic algorithms with side-channel attack protection, true random numbers generator and secure external storage controller. The ASIL D compliant ARC SEM130FS processor adds safety-critical hardware features such as dual-core lockstep to meet stringent automotive safety requirements. Both the ARC SEM130FS processor and the automotive tRoot HSM are supported by comprehensive safety documentation, including Failure Modes, Effects and Diagnostic Analysis (FMEDA) reports to facilitate chip-level and system-level ISO 26262 ASIL B or ASIL D compliance.

“Security attacks on safety-critical ADAS, telematics, radar, V2X communications and industrial systems are increasing, and developers need to achieve a high level of security while eliminating points of failure,” said Wolfgang Ruf, Product Manager semiconductor at SGS-TÜV Saar. Synopsys extends its DesignWare tRoot HSM and ARC SEM processor IP solutions to add functional safety mechanisms that help developers more easily deliver SoCs that meet customer ASIL requirements and ensure high-value data and communications are protected from attack.”

Synopsys’ DesignWare tRoot HSM with an integrated root of trust provides developers with a Trusted Execution Environment (TEE), an essential component of pre-integrated, pre-validated information security and functional safety solutions. The automotive tRoot HSM also incorporates various safety mechanisms such as hardware redundancy, register error detection code (EDC), memory error correction code (ECC), watchdog timers, and self-checking comparators for the entire system. In addition, the automotive tRoot HSM protects sensitive information and data processing in the connected car with features including secure boot, commissioning, firmware updates and key management.

The Synopsys DesignWare ARC SEM130FS processor features Synopsys’ SecureShield™ technology, which helps developers protect safety-critical systems from software, hardware, and side-channel attacks, and is ASIL D compliant, covering random hardware failures and the system development process. The processor integrates multiple hardware safety features, including dual-core lockstep, memory and interface error-correcting code (ECC), internal register transient fault protection, diagnostic error injection, and an integrated self-test safety monitor. The SEM130FS processor is supported by the certified ASIL D compliant ARC MetaWare Safety Development Kit, which simplifies the workload of ISO 26262 compliant software development, debugging and optimization. To assist developers in reaching the target ASIL, the VC Functional Safety Manager provides ARC FMEDA (Failure Mode Effects and Diagnostic Analysis) reports, while the Z01X fault simulation solution provides a complete fault model to meet ISO 26262 fault injection testing requirements.

“As security threats to connected vehicles continue to increase, the combination of integrated SoC-level functional safety and information security capabilities can help minimize malicious intent in automotive systems,” said John Koeter, senior vice president of IP marketing and strategy at Synopsys. Risk of attacks and data breaches. Synopsys’ new ARC SEM130FS and automotive tRoot HSM integrate specific hardware functional safety and information security features to enable developers to meet ISO 26262 requirements and protect vehicle sensitive data and communications.”

Synopsys’ broad portfolio of DesignWare IP cores includes logic libraries, embedded memory, IO, PVT sensors, embedded test, analog IP, interface IP, security IP, embedded processors and subsystems. To accelerate prototyping, software development, and integration of IP cores into silicon, the Synopsys IP Core Accelerated Program offers IP Core Prototyping Kits, IP Core Software Development Kits, and IP Core Subsystems. Extensive investment in IP core quality, comprehensive technical support allows designers to reduce integration risk and accelerate time to market.

Availability and other resources

The DesignWare ARC SEM130FS processor is planned for Q2 2021, and the DesignWare tRoot HSM IP for automotive applications is planned for Q3 2021.

Assessment Information:

Development and evaluation of the ASIL B and ASIL D compliant ARC SEM130FS processor designed to address ASIL B and ASIL D random hardware failures and ASIL D system failures.

Development and evaluation of an ASIL B compliant automotive tRoot HSM designed to address ASIL B random hardware failures and ASIL D system failures.

The ASIL D Compliant ARC MetaWare Safety Development Kit is ISO 26262-8 2018 certified and ASIL D compliant for the development of safety related software up to ASIL D.

The Links:   LQ104V1DG61 HC16203-A