“While gate pitch (GP) and fin pitch (FP) scaling continues to bring higher performance and lower power consumption to FinFET platforms, at 5nm and beyond, both parasitic capacitance and resistance control and implementation are compromised. Higher transistor performance becomes more challenging.
Author: Dr. Assawer Soussou, semiconductor Process and Integration Engineer, Coventor (a company of Lam Group)
While gate pitch (GP) and fin pitch (FP) scaling continues to bring higher performance and lower power consumption to FinFET platforms, at 5nm and beyond, both parasitic capacitance and resistance control and implementation are compromised. Higher transistor performance becomes more challenging.
In collaboration with the Belgian Microelectronics Research Center (imec), Lam Group used SEMulator3D® virtual manufacturing technology to explore an end-to-end solution, using circuit simulation to better understand the impact of process variations. For the first time, we have developed a method to couple SEMulator3D with a BSIM compact model to evaluate the impact of process variations on circuit performance.
The purpose of this research is to optimize the source-drain size and sidewall thickness of advanced node FinFET designs to increase speed and reduce power consumption. To this end, we compared FinFET inverter structures with three different epitaxial (epi) growth shapes and source-drain Si etch depths (Figure 1), investigated the effect of variation in sidewall thickness of low-k materials, and determined FinFET sidewall thickness and source-drain epitaxial shape combination for optimal performance.
Figure 1. Comparison of key process steps for the three structures
Figure 2 illustrates the methodology of this study. We use three software for modeling: SEMulator3D, BSIM Compact Modeling, and Spectre® Circuit Simulation. First import a GDS input file into SEMulator3D for process simulation and RC netlist extraction. Various data, including geometric and parasitic data, are then extracted from SEMulator3D to create an annotated RC netlist. This netlist is then coupled with the BSIM compact front-end-of-line (FEOL) device model and imported into the Spectre circuit simulation model. This Spectre model was then used to simulate the speed and power consumption of the three different inverters being evaluated.
Figure 2. Flow chart of the research methodology
Figure 3 shows the power dissipation as a function of frequency for the three structures (at different drain-to-drain voltages and sidewall thicknesses). We noticed a similar power-speed trend for all epitaxial shape geometries at different drain-to-drain voltages: increasing sidewall thickness resulted in lower power dissipation. Each epitaxial size has an optimal sidewall thickness that yields maximum speed and optimal Reff × Ceff value (effective resistance value x effective capacitance value). At various sidewall thicknesses, there is a specific epitaxial shape that also provides the highest overall performance. We also investigated the source-drain access resistance (S/DR) and gate-to-source-drain (GT-S/D) capacitance of the three structures at the optimal sidewall thickness for NMOS and PMOS structures in order to better understand the graph Results reported in 3.
Figure 3. Power consumption-speed comparison of three inverters at drain voltages from 0.5V to 1V (a) and power consumption-speed comparison with amplified drain voltage equal to 0.7V (b)
This modeling approach provides valuable guidance on the impact of FinFET process variations on sub-5nm device and circuit performance. We coupled SEMulator3D with BSIM compact modeling and Spectre circuit simulation via RC netlist extraction to successfully evaluate and compare the effects of three different inverter geometries (using different sidewall thicknesses) process flow variations to achieve optimal Transistor performance, the effects of inter-drain voltage and low-k material sidewall variations on speed and power performance are also explored.
Original link: https://www.coventor.com/blog/future-finfets-5nm-beyond-combined-process-circuit-modeling-estimate-performance-next-generation-semiconductors/